module dig_core(clk, rst_n, Xmeas, accel_vld, cfg_data, 
		frm_rdy, clr_rdy,eep_rd_data, eep_cs_n, eep_r_w_n, 
		eep_addr, chrg_pmp_en, dst,	wrt_duty, snd_rsp);


input clk,rst_n,accel_vld,frm_rdy;
input [13:0] Xmeas;
input [23:0] cfg_data;
input [13:0] eep_rd_data;


output [13:0] dst;
output clr_rdy;
output eep_r_w_n;
output eep_cs_n;
output chrg_pmp_en;
output [1:0] eep_addr;
output wrt_duty;
output snd_rsp;


wire [1:0] BoothSel;
typedef enum logic [2:0] {PrevErr2Src0, SumErr2Src0, DutyWrk2Src0, EEP2Src0,
                          Xset2Src0, posAck2Src0, zero2Src0} src0sel_t;
typedef enum logic [2:0] {P2Src1, MultRes2Src1, Xmeas2Src1, CfgData2Src1,
                          Err2Src1, zero2Src1} src1sel_t;

src1sel_t src1sel;
src0sel_t src0sel;


dig_dp iDP(.clk(clk), .rst_n(rst_n), .Xmeas(Xmeas), 
		.cfg_data(cfg_data[13:0]), .eep_rd_data(eep_rd_data), 
		.src1sel(src1sel), .src0sel(src0sel), .cmplmnt(cmplmnt), 
		.saturate(saturate), .dst2P(dst2P), .dst2R(dst2R), .dst2Err(dst2Err), 
		.dst2PrevErr(dst2PrevErr), .dst2SumErr(dst2SumErr), 
		.dst2DutyWrk(dst2DutyWrk), .dst2Xset(dst2Xset), .dst(dst), 
		.BoothSel(BoothSel));


dig_sm iSM(.clk(clk), .rst_n(rst_n), .accel_vld(accel_vld), 
			.eep_cs_n(eep_cs_n), .eep_r_w_n(eep_r_w_n), .eep_addr(eep_addr), 
			.src0sel(src0sel), .src1sel(src1sel), .cmplmnt(cmplmnt), 
			.saturate(saturate), .dst2P(dst2P), .dst2R(dst2R), 
			.dst2Err(dst2Err), .dst2PrevErr(dst2PrevErr), 
			.dst2SumErr(dst2SumErr), .dst2DutyWrk(dst2DutyWrk), 
			.dst2Xset(dst2Xset), .wrt_duty(wrt_duty), .BoothSel(BoothSel), 
			.chrg_pmp_en(chrg_pmp_en), .cfg_data(cfg_data[19:16]), 
			.strt_tx(snd_rsp), .clr_rdy(clr_rdy), .frm_rdy(frm_rdy));



endmodule
